Circuits--Sequential--Registers_1

1.4-bit shift register

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    
    always@(posedge clk or posedge areset)
        begin
            if(areset)
                q<=4'b0;
            else if(load)
              q<=data;
            else if(ena)
                q<={1'b0,q[3:1]};  //右移一位
            else
                q<=q;
        end

endmodule

2.Left/right rotator

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
    
 
    always@(posedge clk)
        begin
            if(load)
                q<=data;
            else
                begin
                    case(ena)
                        2'b00:	q<=q;
                        2'b01:	q<={q[0],q[99:1]};
                        2'b10:	q<={q[98:0],q[99]};
                        2'b11:	q<=q;          		
                    endcase
                end
        end

endmodule

3.Left / right arithmetic 

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    
    always@(posedge clk)
        begin
            if(load)
                q<=data;
            else if(ena)
                begin
                    case(amount)
                        2'b00:	q<={q[62:0],1'b0}; 
                        2'b01:	q<={q[55:0],8'b0};
                        2'b10:	q<={q[63],q[63:1]};  //保留符号位
                        2'b11:	q<={{8{q[63]}},q[63:8]};
                    endcase
                end
        end

endmodule

4.5-bit LFSR

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
    
    always@(posedge clk)
        begin
            if(reset)
                q<=5'h1;
            else
                begin
                    q[4]<=q[0]^1'b0;
                    q[3]<=q[4];
                    q[2]<=q[3]^q[0];
                    q[1]<=q[2];
                    q[0]<=q[1];
                end
        end

endmodule