1. Lemmings2
module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter left = 2'b0;
parameter right = 2'b1;
parameter hleft = 2'b10;
parameter hright = 2'b11;
reg[1:0] state;
reg[1:0] next_state;
wire[1:0] p;
assign p = {bump_left,bump_right};
always @(*) begin
case(state)
left:
begin
if (ground == 1'b0) begin
next_state = hleft;
end
else if ((p == 2'b10)||(p == 2'b11)) begin
next_state = right;
end
else begin
next_state = left;
end
end
right:
begin
if (ground == 1'b0) begin
next_state = hright;
end
else if ((p == 2'b01)||(p == 2'b11)) begin
next_state = left;
end
else begin
next_state = right;
end
end
hleft:
begin
if (ground == 1'b0) begin
next_state = hleft;
end
else begin
next_state = left;
end
end
hright:
begin
if(ground == 1'b0)
next_state = hright;
else
next_state = right;
end
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) begin
state <= left;
end
else state <= next_state;
end
assign walk_left = (state == left);
assign walk_right = (state == right);
assign aaah =((state == hleft)|(state == hright));
endmodule
