33.异步FIFO IP核的配置、调用与仿真

（1）异步FIFO的配置过程：

ps：异步fifo相比较同步fifo少一个实际深度

（2）异步FIFO的调用:

module dcfifo
(
    input               wr_clk          ,
    input               rd_clk          ,
    input       [7:0]   data_in         ,
    input               wr_en           ,
    input               rd_en           ,
    
    output      [15:0]  data_out        ,
    output              full            ,
    output              empty           ,
    output      [6:0]   rd_data_count   ,
    output      [7:0]   wr_data_count     
);

dcfifo_8x256_to_16x128 dcfifo_8x256_to_16x128_inst (
  .wr_clk                   (wr_clk         ),                // input wire wr_clk
  .rd_clk                   (rd_clk         ),                // input wire rd_clk
  .din                      (data_in        ),                      // input wire [7 : 0] din
  .wr_en                    (wr_en          ),                  // input wire wr_en
  .rd_en                    (rd_en          ),                  // input wire rd_en
  .dout                     (data_out       ),                    // output wire [15 : 0] dout
  .full                     (full           ),                    // output wire full
  .empty                    (empty          ),                  // output wire empty
  .rd_data_count            (rd_data_count  ),  // output wire [6 : 0] rd_data_count
  .wr_data_count            (wr_data_count  )  // output wire [7 : 0] wr_data_count
);

endmodule

（3）异步FIFP仿真文件代码：

`timescale 1ns / 1ps

module dcfifo_tb;

reg         wr_clk          ;
reg         rd_clk          ;
reg [7:0]   data_in         ;
reg         wr_en           ;
reg         rd_en           ;
reg         reset_n         ;
reg [1:0]   cnt             ;
reg         full_reg0       ;
reg         full_reg1       ;

wire [15:0] data_out        ;
wire        full            ;
wire        empty           ;
wire [6:0]  rd_data_count   ;
wire [7:0]  wr_data_count   ;

//50MHz读时钟
    initial wr_clk = 1'd1;
    always #10 wr_clk = ~wr_clk;
    
//25MHz写时钟   
    initial rd_clk = 1'd1;
    always #20 rd_clk = ~rd_clk;
    
//复位信号
    initial begin 
        reset_n <= 1'd0;
        #15;
        reset_n <= 1'd1;
        #100_000;
        $stop;
    end
    
//cnt信号    
    always@(posedge wr_clk or negedge reset_n)
        if(!reset_n)
            cnt <= 2'd0;
        else if(cnt == 2'd3)
            cnt <= 2'd0;
        else    
            cnt <= cnt + 2'd1;
            
//wr_en信号
    always@(posedge wr_clk or negedge reset_n)
        if(!reset_n)
            wr_en <= 1'd0;
        else if((cnt == 2'd3) && (rd_en == 1'd0))
            wr_en <= 1'd1;
        else 
            wr_en <= 1'd0;
            
//data_in信号
    always@(posedge wr_clk or negedge reset_n)
        if(!reset_n)
            data_in <= 8'd0;
        else if((data_in == 8'd255) && (wr_en == 1'd1))
            data_in <= 8'd0;
        else if(wr_en == 1'd1)
            data_in <= data_in + 8'd1;
        else    
            data_in <= data_in;
            
//full_reg0、full_reg1信号设计
    always@(posedge rd_clk or negedge reset_n)
        if(!reset_n)begin
            full_reg0 <= 1'd0;
            full_reg1 <= 1'd0;      
        end
        else begin
            full_reg0 <= full;
            full_reg1 <= full_reg0;
        end
            

//rd_en信号
    always@(posedge rd_clk or negedge reset_n)
        if(!reset_n)
            rd_en <= 1'd0;
        else if(full_reg1 && (wr_en == 1'd0))
            rd_en <= 1'd1;
        else if(empty)
            rd_en <= 1'd0;
        else 
            rd_en <= rd_en;
            
            
dcfifo dcfifo_inst
(
    .wr_clk          (wr_clk  ),
    .rd_clk          (rd_clk  ),
    .data_in         (data_in ),
    .wr_en           (wr_en   ),
    .rd_en           (rd_en   ),
    
    .data_out        (data_out     ),
    .full            (full         ),
    .empty           (empty        ),
    .rd_data_count   (rd_data_count),
    .wr_data_count   (wr_data_count)  
);



endmodule

（4）仿真波形：