【VERILOG】输入脉冲下降沿触发输出一组双脉冲 （附带testbench）

`timescale 1ns/1ps

module pulseturn(
				clk,
				reset_n,
				in,
				out
);

	input 		clk;
	input 		in;
	input 		reset_n;
	output 	reg	out;
	
	reg [7:0]	cnt;
	reg [1:0]   data_in;
	
	assign pos_edge = ~data_in[1]&data_in[0];
	assign neg_edge = data_in[1]&~data_in[0];
	
	always@(posedge clk or negedge reset_n )
	if(reset_n == 1'b0)
		begin 	
			data_in <= 2'b0;
		end
	else
		begin
			data_in <= {data_in[0],in};
		end
	
	
	
	
	always@(posedge clk or negedge reset_n )
	if(reset_n == 1'b0)
		begin 	
				out 	<= 1'b0;
				cnt 	<= 8'd0;
		end
	else if(neg_edge == 1'b1 )
		begin
				cnt <= 8'd0;
		end
	else 
		begin
				cnt <= cnt +1'b1;
		end
		
		
	always@(posedge clk or negedge reset_n)
	if(cnt == 8'd49)
		begin
			out <=1'b1;
		end
	else if(cnt == 8'd99)
		begin
			out <=1'b0;
		end
	else if(cnt == 8'd149)
		begin
			out <=1'b1;
		end
	else if(cnt == 8'd199)
		begin
			out <=1'b0;
		end
				
endmodule

testbench

module pulseturn_tb;

reg  clk,reset_n,in;

reg [7:0] cnnt;
wire out;
pulseturn  pulseturn(
				.clk(clk),
				.reset_n(reset_n),
				.in(in),
				.out(out)
);


initial begin
		clk <= 0;
		reset_n <= 0;
		in <= 0;
		cnnt = 8'd0;
		#10 reset_n <= 1;
	forever #10
		clk <= ~clk;
	end	



	always@(posedge clk)
	begin
		cnnt <= cnnt+1'b1;
	
	end
	
	always@(posedge clk )
	if(cnnt == 8'd5)
		begin
			in <=1'b1;
		end
	else if(cnnt == 8'd30)
		begin
			in <=1'b0;
		end


endmodule

测试波形