「HDLBits题解」Latches and Flip-Flops

本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益

题目链接：Dff - HDLBits

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    always @(posedge clk) begin
        q <= d ; 
    end

endmodule

题目链接：Dff8 - HDLBits

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk) begin
        q <= d ; 
    end

endmodule

题目链接：Dff8r - HDLBits

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk) begin
        if (reset) q <= 0 ; 
        else q <= d ; 
    end

endmodule

题目链接：Dff8p - HDLBits

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always @(negedge clk) begin
        if (reset) q <= 8'h34 ; 
        else q <= d ; 
    end

endmodule

题目链接：Dff8ar - HDLBits

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk or posedge areset) begin
        if (areset) q <= 0 ; 
        else q <= d ; 
    end

endmodule

题目链接：Dff16e - HDLBits

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output reg [15:0] q
);
    always @(posedge clk) begin
        if (!resetn) q <= 0 ; 
        else begin
        	if (byteena[1]) q[15:8] <= d[15:8] ;
        	if (byteena[0]) q[7:0] <= d[7:0] ;
        end
    end

endmodule

题目链接：Exams/m2014 q4a - HDLBits

module top_module (
    input d, 
    input ena,
    output q
);
    always @(*) begin
        if (ena) q <= d ; 
        else q <= q ; 
    end

endmodule

题目链接：Exams/m2014 q4b - HDLBits

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q
); 
    always @ (posedge clk or posedge ar) begin 
        if (ar) q <= 0 ; 
        else q <= d ; 
    end

endmodule

题目链接：Exams/m2014 q4c - HDLBits

module top_module (
    input clk,
    input d, 
    input r,   // asynchronous reset
    output q
); 
    always @ (posedge clk) begin 
        if (r) q <= 0 ; 
        else q <= d ; 
    end

endmodule

题目链接：Exams/m2014 q4d - HDLBits

module top_module (
    input clk,
    input in, 
    output out
);
    wire gate_out ; 

    assign gate_out = out ^ in ;

    always @(posedge clk) begin
        out <= gate_out ; 
    end

endmodule

题目链接：Mt2015 muxdff - HDLBits

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q
);
    wire mux_out ; 
    assign mux_out = L ? r_in : q_in ;

    always @(posedge clk) begin
        Q <= mux_out ; 
    end

endmodule

题目链接：Exams/2014 q4a - HDLBits

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q
);
    wire mux_out ; 
    assign mux_out = L ? r_in : q_in ;

    always @(posedge clk) begin
        Q <= mux_out ; 
    end

endmodule

题目链接：Exams/ece241 2014 q4 - HDLBits

module top_module (
    input clk,
    input x,
    output z
); 
    wire Q1, Q1n, Q2, Q2n, Q3, Q3n ; 
    wire g1o, g2o, g3o ; 

    assign g1o = x ^ Q1 ; 
    assign g2o = x & Q2n ; 
    assign g3o = x | Q3n ; 

    myDFF u1(clk, g1o, Q1, Q1n) ;
    myDFF u2(clk, g2o, Q2, Q2n) ;
    myDFF u3(clk, g3o, Q3, Q3n) ;

    assign z = ~(Q1 | Q2 | Q3) ;

endmodule

module myDFF (
    input clk, 
    input d, 
    output reg q, 
    output qn 
); 
    assign qn = ~q ;
    always @(posedge clk) begin
        q <= d ; 
    end

endmodule

题目链接：Exams/ece241 2013 q7 - HDLBits

module top_module (
    input clk,
    input j,
    input k,
    output reg Q
); 
    always @(posedge clk) begin
        if (!j && !k) Q <= Q ; 
        else if (!j && k) Q <= 0 ; 
        else if (j && !k) Q <= 1 ; 
        else Q <= ~Q ; 
    end

endmodule

题目链接：Edgedetect - HDLBits

module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] pedge
);
    reg [7:0] temp ; 

    always @(posedge clk) begin
        integer i ; 
        for (i = 0 ; i <= 7 ; i = i + 1) 
            if (!temp[i] && in[i])
                pedge[i] <= 1 ; 
            else 
                pedge[i] <= 0 ; 
        temp <= in ; 
    end 

endmodule

题目链接：Edgedetect2 - HDLBits

module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] anyedge
);
    reg [7:0] temp ; 

    always @(posedge clk) begin
        integer i ; 
        for (i = 0 ; i <= 7 ; i = i + 1) 
            if (temp[i] != in[i])
                anyedge[i] <= 1 ; 
            else 
                anyedge[i] <= 0 ; 
        temp <= in ; 
    end 

endmodule

题目链接：Edgecapture - HDLBits

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    reg [31:0] temp ; 
    integer i ;

    always @(posedge clk) begin
        if (reset) out <= 0 ; 
        else 
            for (i = 0 ; i <= 31 ; i ++ ) 
                if (temp[i] && !in[i]) 
                    out[i] <= 1 ; 
        temp <= in ; 
    end

endmodule

题目链接：Dualedge - HDLBits

module top_module (
    input clk,
    input d,
    output q
);  
    reg t1, t2 ; 

    always @(posedge clk) begin
        t1 <= d ; 
    end

    always @(negedge clk) begin
        t2 <= d ; 
    end

    assign q = clk ? t1 : t2 ; 

endmodule