dut.v
module counter (
input clk,rstn,load,
input [1:0] in,
output reg [1:0] out
);
// always @(posedge clk ) begin
// always @(negedge clk ) begin
always @(posedge clk or negedge rstn) begin
if(!rstn) begin
out <= 2'd0;
end
else if(load)begin
out <= in;
end
else begin
out <= out +1'b1 ;
end
end
endmodule
sim_top.sv
module sim_top (
);
reg clk ;
reg rstn;
reg load;
reg [1:0] in ;
wire out ;
task task00();
begin
rstn = 1'b0; #100ns;
rstn = 1'b1;
load = 1'b1;
repeat(10)begin
in = in+1'b1;
#10 ;clk = ~clk;
#10 ;clk = ~clk;
end
end
endtask
task task01();
begin
rstn = 1'b0; #100ns;
rstn = 1'b1;
load = 1'b0;
repeat(10)begin
in = in+1'b1;
#10 ;clk = ~clk;
#10 ;clk = ~clk;
end
end
endtask
initial begin
clk =1'd0;
rstn =1'd0;
load =1'd0;
in =2'd0;
#100ns;
task00;
#100ns;
task01;
#100ns;
end
counter dut (
.clk (clk ),
.rstn (rstn),
.load (load),
.in (in ),
.out (out )
);
initial begin
$fsdbDumpfile("verilog.fsdb");
$fsdbDumpvars();
$vcdpluson;
$display("fsdbDumpfilrs is start at %d",$time);
#1e9;
$finish;
end
endmodule
仿真效果
在上电初始阶段
rstn和load为低电平,输出位0
在load使能之后
时钟上升沿采样输出IN的值
经过复位之后,输出为0
这次将load置低
电路进行自加1功能