Xilinx FPGA 管脚的默认电平配置方法 XDC约束

未使用的引脚，XDC约束

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

其他已使用的引脚，XDC约束

set_property PULLDOWN true [get_ports RF28V_EN]
set_property PULLDOWN true [get_ports RF5V_EN]
set_property PULLUP true [get_ports LNA_EN]
set_property PULLDOWN true [get_ports PA_EN]
set_property PULLDOWN true [get_ports bypass_EN]
set_property PULLDOWN true [get_ports C1]
set_property PULLDOWN true [get_ports C2]
set_property PULLDOWN true [get_ports C3]
set_property PULLDOWN true [get_ports C4]