1，hardware design
ultraembedded (ultraembedded) / Repositories · GitHub
2，an implement
3， book
https://github.com/cnrv/riscv-soc-book
4， 蜂鸟开源
https://github.com/SI-RISCV/e200_opensource
5，内容比较丰富
https://github.com/PulseRain/Reindeer
6，
7，design a sim for riscv
GitHub - plctlab/writing-your-first-riscv-simulator: 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
8，
GitHub - shzhxh/xv6-riscv-book-CN: xv6-riscv-book中译版
9，collection
GitHub - riscv-steel/riscv-steel: Free and open collection of RISC-V IP.
what？
10，GitHub - HUST-OS/tornado-os: 异步内核就像风一样快！
11，a riscv model
https://github.com/ArchC/riscv
12，a risvc model with systemc
https://github.com/mariusmm/RISC-V-TLM
13, verification for 蜂鸟
https://github.com/panweitao/riscvv
14，
https://github.com/anycore/anycore-riscv-src
15，课程资料 arch
https://github.com/ChampionNan/RISCV
16，
https://github.com/janvrany/riscv-debian
17，simple riscv
https://github.com/qmn/riscv-invicta
18，
https://github.com/cjhonlyone/picorv32_Xilinx
19，
https://github.com/open-design/riscv-soc-cores
20,
GitHub - PulseRain/Reindeer: PulseRain Reindeer - RISCV RV32I[M] Soft CPU
21, very simple risc-v
GitHub - qmn/riscv-invicta: A simple RISC-V core, described with Verilog
22,
23,
GitHub - open-design/riscv-soc-cores
24, 64-bit core
GitHub - eminfedar/fedar-f1-rv64im: 5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
25, vector impl
GitHub - ic-lab-duth/RISC-V-Vector: Vector processor for RISC-V vector ISA
26, coverage
GitHub - riscv-verification/riscvISACOV: SystemVerilog Functional Coverage for RISC-V ISA
27, Chinese tutorial
https://github.com/sunshaoce/learning-riscv
28, impl of riscv
https://github.com/thinkoco/de10-nano-riscv/tree/master
29, asm of riscv
GitHub - zju-stu-lizheng/-riscv-: 浙江大学计算机组成riscv——实验部分（vivado2020）
30, one night impl
31,
GitHub - syntacore/scr1: SCR1 is a high-quality open-source RISC-V MCU core in Verilog
