1.原理
![](https://img-blog.csdnimg.cn/direct/eaa2495969df4132b1a492bed2cda7cc.png)
![](https://img-blog.csdnimg.cn/direct/22939651b9934cfe9626633bc2a1dead.png)
![](https://img-blog.csdnimg.cn/direct/b2a3a56586ca4de294bdca1a38f44c9e.png)
2.代码
2.1 half_adder.v
module half_adder
(
input wire in_1 ,
input wire in_2 ,
output wire sum ,
output wire count
);
assign {count,sum}=in_1+in_2;
endmodule
2.2 tb_half_adder.v
`timescale 1ns/1ns
module tb_half_adder();
reg in_1;
reg in_2;
wire sum;
wire count;
initial
begin
in_1<=1'b0;
in_2<=1'b0;
end
always# 10 in_1={$random}%2;
always# 10 in_2={$random}%2;
initial
begin
$timeformat(-9,0,"ns",6);
$monitor("@time %t:in_1=%b,in_2=%b,sum=%b,count=%b",$time,in_1,in_2,sum,count);
end
half_adder half_adder_inst
(
.in_1 (in_1),
.in_2 (in_2),
.sum (sum),
.count (count)
);
endmodule
![](https://img-blog.csdnimg.cn/direct/400cd7ba83b545a5864624edf6e6a120.png)